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fn7346 rev 1.00 page 1 of 11 may 23, 2005 fn7346 rev 1.00 may 23, 2005 el5524, el5624, e l5724, el5824 integrated buffers with vcom datasheet the el5524, el5624, el5724, and el5824 integrate a number of gamma reference buffers with a single v com amplifier. the el5524 cont ains 4 gamma buffers, the el5624 contains 6, the el5724 contains 8, and the el5824 contains 10. each gamma buffe r has a bandwidth of 12mhz and features a slew rate of 15v/s. the output current is rated at 30ma conti nuous, 140ma peak. the v com amplifiers are rated for 60ma conti nuous output current and 200ma peak. they also feature higher slew rate and bandwidth for use in error cancellation circuits. the el5524 is available in the 14-pin htssop package, the el5624 in the 20-pin htssop package, the el5724 in the 24-pin htssop package, and t he el5824 in the 28-pin htssop package. all are specif ied for operation over the -40c to +85c temperature range. features ? 4 x gamma buffers (el5524) ? 6 x gamma buffers (el5624) ? 8 x gamma buffers (el5724) ? 10 x gamma buffers (el5824) ?single v com amplifier ?140ma max v com output current ? low power - 5.4ma (el5524) - 6.8ma (el5624) - 8.3ma (el5724) - 9.5ma (el5824) ? pb-free plus anneal available (rohs compliant) applications ?tft-lcd displays ? flat panel monitors ? notebook displays ?lcd-tvs ordering information part number package tape & reel pkg. dwg. # el5524ire 14-pin htssop - mdp0048 el5524ire-t7 14-pin htssop 7" mdp0048 el5524ire-t13 14-pin htssop 13" mdp0048 el5524irez (see note) 14-pin htssop (pb-free) - mdp0048 el5524irez-t7 (see note) 14-pin htssop (pb-free) 7" mdp0048 el5524irez-t13 (see note) 14-pin htssop (pb-free) 13" mdp0048 el5624ire 20-pin htssop - mdp0048 el5624ire-t7 20-pin htssop 7" mdp0048 EL5624IRE-T13 20-pin htssop 13" mdp0048 el5624irez (see note) 20-pin htssop (pb-free) - mdp0048 el5624irez-t7 (see note) 20-pin htssop (pb-free) 7" mdp0048 el5624irez-t13 (see note) 20-pin htssop (pb-free) 13" mdp0048 el5724ire 24-pin htssop - mdp0048 el5724ire-t7 24-pin htssop 7" mdp0048 el5724ire-t13 24-pin htssop 13" mdp0048 el5724irez (see note) 24-pin htssop (pb-free) - mdp0048 el5724irez-t7 (see note) 24-pin htssop (pb-free) 7" mdp0048 el5724irez-t13 (see note) 24-pin htssop (pb-free) 13" mdp0048 el5824ire 28-pin htssop - mdp0048 el5824ire-t7 28-pin htssop 7" mdp0048 el5824ire-t13 28-pin htssop 13" mdp0048 el5824irez (see note) 28-pin htssop (pb-free) - mdp0048 el5824irez-t7 (see note) 28-pin htssop (pb-free) 7" mdp0048 el5824irez-t13 (see note) 28-pin htssop (pb-free) 13" mdp0048 note: intersil pb-free products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are ro hs compliant and compatible wit h both snpb and pb-free soldering operations. intersil pb-free product s are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. ordering information (continued) part number package tape & reel pkg. dwg. #
el5524, el5624, el5724, el5824 fn7346 rev 1.00 page 2 of 11 may 23, 2005 pinouts el5524 (14-pin htssop) top view el5624 (20-pin htssop) top view el5724 (24-pin htssop) top view el5824 (28-pin htssop) top view 1 2 3 4 14 13 12 11 5 6 7 10 9 8 vin1 vin2 vin3 vin4 vs+ vinp vinn vout1 vout2 vout3 vout4 vs- vout nc thermal pad 1 2 3 4 16 15 14 13 5 6 7 12 11 9 8 10 20 19 18 17 vin1 vin2 vin3 vin4 vs+ vs+ vin5 vout1 vout2 vout3 vout4 vs- vs- vout5 vin6 vinp vinn vout6 vout nc thermal pad 1 2 3 4 16 15 14 13 5 6 7 12 11 9 8 10 20 19 18 17 24 23 22 21 vin1 vin2 vin3 vin4 vin5 vs+ vs+ vout1 vout2 vout3 vout4 vout5 vs- vs- vin6 vin7 vin8 vout6 vout7 vout8 vinp vinn vout nc thermal pad 1 2 3 4 28 27 26 25 5 6 7 24 23 22 8 21 9 10 20 19 11 12 13 18 17 16 14 15 vin1 vin2 vin3 vin4 vin5 vin6 vs+ vout1 vout2 vout3 vout4 vout5 vout6 vs- vs+ vin7 vin8 vs- vout7 vout8 vin9 vin10 vout9 vout10 vinp vinn vout nc thermal pad
el5524, el5624, el5724, el5824 fn7346 rev 1.00 page 3 of 11 may 23, 2005 note: all parameters having min/ max specifications are guarantee d. typ values are for information purposes only. unless otherwi se noted, all tests are at the specified temperature and are pulsed tests, therefor e: t j = t c = t a absolute maximum ratings (t a = 25c) supply voltage between v s + and v s - . . . . . . . . . . . . . . . . . . . .+18v input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . v s - -0.5v, v s + +0.5v maximum continuous output current (buffer) . . . . . . . . . . . . 30ma maximum continuous output current (v com ) . . . . . . . . . . . . 60ma power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see curves maximum die temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125c storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c operating conditions . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +85c caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. electrical specifications v s + = +15v, v s - = 0, r l = 10k ? , c l = 10pf to 0v, gain of v com = 1, rlv cm = 1k ? and t a = 25c unless otherwise specified parameter description conditions min typ max unit input characteristics (reference buffers) v os input offset voltage v cm = 0v 2 14 mv tcv os average offset voltage drift (note 1) 5 v/ ? c i b input bias current v cm = 0v 2 50 na r in input impedance 1g ? c in input capacitance 1.35 pf a v voltage gain 1v ?? v out ?? 14v 0.992 1.008 v/v input characteristics (v com amplifier) v os input offset voltage v cm = 7.5v 1 15 mv tcv os average offset voltage drift (note 1) 5 v/ ? c i b input bias current v cm = 7.5v 2 50 na r in input impedance 1g ? c in input capacitance 1.35 pf v reg load regulation v com = 1.5v, -60ma < i l < 60ma -20 +20 mv a vol open loop gain r l = 1k ? 55 75 db cmrr common rejection ratio 45 70 db output characteristics (reference buffers) v ol output swing low i l = 7.5ma 50 150 mv v oh output swing high i l = 7.5ma 14.85 14.95 v i sc short circuit current r l = 10 ? 120 140 ma output characteristics (v com amplifier) v ol output swing low i l = -7.5ma 50 150 mv v oh output swing high i l = +7.5ma 14.85 14.95 v i sc short circuit current r l = 10 ? 180 200 ma power supply performance psrr power supply rejection ratio reference buffer v s from 4.5v to 15.5v 55 80 db v com buffer, v s from 4.5v to 15.5v 55 80 db i s total supply current el5524 (no load) 5.4 7 ma el5624 (no load) 6.8 8.5 ma el5724 (no load) 8.3 11 ma el5824 (no load) 9.5 12.5 ma
el5524, el5624, el5724, el5824 fn7346 rev 1.00 page 4 of 11 may 23, 2005 dynamic performance ( buffer amplifiers) sr slew rate (note 2) -4v ?? v out ?? 4v, 20% to 80% 7 15 v/s t s settling to +0.1% (a v = +1) (a v = +1), v o = 2v step 250 ns bw -3db bandwidth r l = 10k ? , c l = 10pf 12 mhz gbwp gain-bandwidth product r l = 10k ? , c l = 10pf 8 mhz pm phase margin r l = 10k ? , c l = 10pf 50 cs channel separation f = 5mhz 75 db dynamic performance (v com amplifiers) sr slew rate (note 2) -4v ?? v out ?? 4v, 20% to 80% 65 90 v/s t s settling to +0.1% (a v = +1) (a v = +1), v o = 6v step 150 ns bw -3db bandwidth r l = 1k ? , c l = 2pf 35 mhz gbwp gain-bandwidth product r l = 1k ? , c l = 2pf 20 mhz pm phase margin r l = 1k ? , c l = 2pf 50 notes: 1. measured over operating temperature range 2. slew rate is measured on rising and falling edges electrical specifications v s + = +15v, v s - = 0, r l = 10k ? , c l = 10pf to 0v, gain of v com = 1, rlv cm = 1k ? and t a = 25c unless otherwise specified (continued) parameter description conditions min typ max unit
el5524, el5624, el5724, el5824 fn7346 rev 1.00 page 5 of 11 may 23, 2005 test circuits pin descriptions el5524 el5624 el5724 el5824 pin name pin function 1 1 1 1 vin1 input 2 2 2 2 vin2 input 3 3 3 3 vin3 input 4 4 4 4 vin4 input 5 5, 6 6, 7 7, 8 vs+ positive supply 6 9 11 13 vinp positive input - v com 7 10 12 14 vinn negative input - v com 8 11 13 15 nc not connected 9 12 14 16 vout output for v com 10 15, 16 18, 19 21, 22 vs- negative supply 11 17 21 25 vout4 output 12 18 22 26 vout3 output 13 19 23 27 vout2 output 14 20 24 28 vout1 output 7 5 5 vin5 input 8 8 6 vin6 input 14 20 24 vout5 output 13 17 23 vout6 output 9 9 vin7 input 10 10 vin8 input 16 20 vout7 output 15 19 vout8 output 11 vin9 input 12 vin10 input 18 vout9 output 17 vont10 output 50 ? 10k ? 10pf v out v in 50 ? 1k ? 2pf v out v in for buffers for v com + -
el5524, el5624, el5724, el5824 fn7346 rev 1.00 page 6 of 11 may 23, 2005 typical performance curves figure 1. frequency response for various r l (buffer) figure 2. frequency response for various c l (buffer) figure 3. psrr vs frequency (buffer) figure 4. output impedance vs frequency (buffer) figure 5. input noise special density vs frequency (buffer) figure 6. overshoot vs load capacitance (buffer) normalized magnitude (db) 20 10 0 -10 -20 -30 100k 1m 10m 100m frequency (hz) v s =7.5v c l =10pf 10k ? 562 ? 150 ? 1k ? ???? ???? ? ? 100pf 1000pf 12pf 47pf psrr (db) 100 80 60 40 20 0 1k 10k 1m 10m frequency (hz) v s =7.5v psrr- psrr+ 100k output impedance ( ? ) 600 480 360 240 120 0 100k 1m 10m 100m frequency (hz) v s =7.5v t a =25c voltage noise (nv/ ? hz) 100 10 1 10k 100k 10m 100m frequency (hz) 1m 80 70 60 50 40 20 0 10 100 1k capacitance (pf) overshoot (%) 30 10 v s =7.5v r l =10k ? v in =100mv
el5524, el5624, el5724, el5824 fn7346 rev 1.00 page 7 of 11 may 23, 2005 figure 7. settling time vs step size (buffer) figure 8. total harm onic distortion + noise vs frequency (buffer) figure 9. output swing vs frequency (buffer) figure 10. frequency response (v com ) figure 11. open loop gain and phase vs frequency figure 12. transient load regulation - sourcing (buffer) typical performance curves (continued) 10 8 6 4 2 -6 -10 200 400 650 settling time (ns) step size (v) -2 -8 0 -4 250 300 350 450 500 550 600 v s =7.5v r l =10k ? c l =12pf 0.018 0.016 0.014 0.012 0.01 0.008 0.006 1k 10k 100k frequency (hz) thd + noise (%) v s =5v r l =10k ? v in =2v p-p 12 10 8 6 4 2 0 10k 100k 1m 10m frequency (hz) v op-p (v) v s =5v r l =10k ? ???? ???? ? ? c l =2pf a v =10 a v =5 a v =1 a v =2 70 50 -10 -30 30 10 1k 100m 10k 100k 1m 10m frequency (hz) gain (db) phase () 0 -72 -288 -360 -144 -216 phase gain v s =5v r f =1k ? r l =1k ? c l =1.5pf 5ma 0v 5ma/div 500mv/div r s =0 ? c l =200pf r s =10 ? c l =4.7nf r s =10 ? c l =1nf 0ma m=1s/div, v s =7.5v, v in =0v
el5524, el5624, el5724, el5824 fn7346 rev 1.00 page 8 of 11 may 23, 2005 figure 13. transient load regulation - sinking (buffer) figure 14. transient load regulation (v com ) figure 15. small signal transient response (buffer) figure 16. large sig nal transient response (buffer) figure 17. small signal transient response (v com ) 1 figure 18. large signal transient reponse (v com ) typical performance curves (continued) 5ma 0v 5ma/div 500mv/div r s =0 ? c l =200pf r s =10 ? c l =4.7nf r s =10 ? c l =1nf 0ma m=1s/div, v s =7.5v, v in =0v 50ma v s =7.5v, r l =200 ??? c l =150pf 0ma -50ma 200ns/div 50mv/div v s =7.5v, r l =10k ??? c l =12pf 1s/div 1v/div v s =7.5v 100ns/div 100mv/div v s =7.5v, r l =1k ??? c l =2pf 100ns/div 1v/div v s =7.5v, r l =1k ??? c l =2pf
el5524, el5624, el5724, el5824 fn7346 rev 1.00 page 9 of 11 may 23, 2005 description of operat ion and application information product description the el5524, el5624, el5724, and el5824 are fabricated using a high voltage cmos process. they exhibit rail to rail input and output capability and have very low power consumption. when driving a load of 10k and 12pf, the buffers have a -3db bandwidth of 12mhz and exhibit 18v/s slew rate. the v com amplifier has a -3db bandwidth of 35mhz and exhibit 80v/s slew rate. input, output, and supply voltage range the el5524, el5624, el5724, and el5824 ar e specified with a single nominal supply voltage from 5v to 15v or a split supply with its total range from 5v to 15v. correct operation i s guaranteed for a supply range from 4.5v to 16.5v. the input common-mode vol tage range of the el5524, el5624, el5724, and el5824 extends 500mv beyond the supply rails. the output s wings of the buffers and v com amplifier typically extend to wit hin 100mv of the positive and negative supply rails with load currents of 5ma. decreasing load currents will extend the output voltage even closer to eac h supply rails. output phase reversal the el5524, el5624, el5724, and el5824 ar e immune to phase reversal as long as the input voltage is limited from v s - - 0.5v to v s + +0.5v. although the de vice's output will not change phase, the input's overv oltage should be avoided. if an input voltage exceeds supply voltage by more than 0.6v, electrostatic protection diode placed in the input stage of the device begin to conduct and overvoltage damage could occur. choice of feedback resistor and gain bandwidth product for v com amplifier for applications that r equire a gain of +1, no feedback resisto r is required. just short the out put pin to the inverting input p in. for gains greater t han +1, the feedback re sistor forms a pole with the parasitic capacitance at the inverting input. as this pole becomes smaller, the amplifier's phase margin is reduced. this causes ringing in the time domain and peaking in the frequency domain. therefore, r f has some maximum value that should not be exceeded fo r optimum perf ormance. if a large value of r f must be used, a small capacitor in the few pico farad range in parallel with r f can help to reduce the ringing and peaking at the ex pense of reducing the bandwidth. as far as the output stage of t he amplifier is concerned, the output stage is also a ga in stage with the load. r f and r g appear in parallel with r l for gains other than +1. as this combination gets smaller, the bandwidth falls off. consequently, r f also has a minimum value that should not be exceeded for optimum perfo rmance. for gain of +1, r f = 0 is optimum. for the gains other t han +1, optimum response is obtained with r f between 1k ? to 5k ? . the v com amplifier has a gain bandwidth product of 20mhz. for gains ? 5, its bandwidth can be pr edicted by the following equation: output drive capability the el5524, el5624, el5724 , and el5824 do not have internal short-circuit protecti on circuitry. the buffers will l imit the short circuit current to 120ma and the v com amplifier will limit the short circuit current to 200ma if the outputs are figure 19. package power dissipation vs ambient temperature figure 20. package power dissipation vs ambient temperature typical performance curves (continued) jedec jesd51-3 low effective thermal conductivity test board 1 0.9 0.6 0.4 0.3 0.2 0.1 0 0 255075100 150 ambient temperature (c) power dissipation (w) 85 0.8 0.5 0.7 125 909mw 800mw 694mw 833mw ? ja =110c/w htssop28 ? ja =120c/w htssop24 ? ja =125c/w htssop20 ? ja =144c/w htssop14 jedec jesd51-7 high effective thermal conductivity test board - htssop exposed diepad soldered to pcb per jesd51-5 3.5 3 2.5 1.5 1 0.5 0 0 255075100 150 ambient temperature (c) power dissipation (w) 125 85 2 2.632w 3.333w 3.030w 2.857w ? ja =35c/w htssop20 ? ja =38c/w htssop14 ? ja =30c/w htssop28 ? ja =33c/w htssop24 gain bw 20mhz = ?
el5524, el5624, el5724, el5824 fn7346 rev 1.00 page 10 of 11 may 23, 2005 directly shorted to the positiv e or the negative supply. if the output is shorted indefinitely, t he power dissipation could eas ily increase such that the par t will be destroyed. maximum reliability is maintained if the output continuous current neve r exceeds 30ma for the buf fers and 60ma for the v com amplifier. these limits are set by the design of the internal metal interconnections. the unused buffers it is recommended that any unu sed buffers should have their inputs tied to ground plane. power dissipation with the high-output drive cap ability of the el5524, el5624, el5724, and el5824, it is po ssible to exceed the 125c absolute-maximum junction tem perature under certain load current conditions. therefore, it is important to calculate the maximum junction temperature for the application to determine if load conditions need to be modified for the buffer to remain in the safe oper ating area. the maximum power dissipation allowed in a package is determined according to: where: ?t jmax = maximum junction temperature ?t amax = maximum ambien t temperature ? ? ja = thermal resistance of the package ?p dmax = maximum power dissipation in the package the maximum power dissipation a ctually produced by an ic is the total quiescent supply curr ent times the tota l power supply voltage, plus the power in t he ic due to the loads, or: when sourcing, and: when sinking. where: ? i = 1 to total number of buffers ?v s = total supply voltage of buffer and v com ?i smax = total quiescent current ?v out i = maximum output volt age of the application ?v out = maximum output voltage of v com ?i load i = load current of buffer ?i la = load current of v com if we set the two p dmax equations equal to each other, we can solve for the r load 's to avoid device ov erheat. the package power dissipation curves provide a convenient way to see if the device will overheat. the maximum safe power dissipation can be found graphically, based o n the package t ype and the ambient temperature. by using t he previous equation, it is a simple matter to see if p dmax exceeds the device's power derating curves. power supply bypassing and printed circuit board layout as with any high frequency devic e, good printed circuit board layout is necessary for optimum perfo rmance. ground plane construction is highly recommended, lead lengths should be as short as possible, and the power supply pins must be well bypassed to reduce the risk of oscillation. for normal single supply operation, where the v s - pin is connected to ground, one 0.1f ceramic capacitor should be placed from the v s + pin to ground. a 4.7f tantalum capacitor should then be connected from the v s + pin to ground. one 4.7f capacitor may be used for multiple devi ces. this same capacitor combination should be placed a t each supply pin to ground if split supplies are to be used. important note: the metal plane used for heat sinking of the device is electrically connect ed to the negative supply potential (v s -). if v s - is tied to ground , the thermal pad can be connected to ground. otherwise, the thermal pad must be isolated from any other power planes. p dmax t jmax - t amax ? ja -------------------------------------------- - = p dmax v s i s ? iv s + ? ? v out i ? i load i ? v s + ? v out ? i la ? C + ? C ? + ? = p dmax v s i s ? iv ? out i ? v s - ? i load i ? v out ? v s - ? i la ? C + ? C ? + ? =
fn7346 rev 1.00 page 11 of 11 may 23, 2005 el5524, el5624, el5724, el5824 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas ll c 2003-2005. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. htssop package outline drawing note: the package drawings shown here may not be the latest vers ions. for the latest revisions, p lease refer to the intersil we bsite at www.intersil.com/design/packages/elantec

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